Synchronous/asynchronous interface circuit and electronic device

ABSTRACT

An exemplary embodiment provides a synchronous/asynchronous interface circuit and an electronic device for coupling an asynchronous circuit block onto a globally synchronous circuit system. A synchronous/asynchronous interface circuit according to an exemplary embodiment of the present invention includes a finite state machine that controls access cycles between a synchronous bus and an asynchronous CPU in an event-driven fashion and a detection circuit that detects beginnings of the access cycles. In interfacing with the asynchronous CPU, the finite state machine controls the access cycles by transiting in states handshaking with the asynchronous CPU. Meanwhile, in interfacing with the synchronous bus, the finite state machine controls the access cycle by transiting in states synchronizing with a global clock supplied from the synchronous bus.

BACKGROUND OF THE INVENTION

1. Field of Invention

An exemplary embodiment of the present invention relates to techniquesof coupling asynchronous circuits onto a synchronous circuit driven by aglobal clock. More particularly, an exemplary embodiment of the presentinvention relates to interface circuits to connect an asynchronouscircuit to a synchronous circuit, and also relates to electronic devicesincluding the asynchronous circuits, synchronous circuits and theinterface circuits.

2. Description of Related Art

It is a minimum requirement for related art synchronous circuits tosettle into the next state within a clock cycle. This means that, in thecritical path, the sum of switching delays of sequential circuits andthe setup time of a combination circuit must be sufficiently smallerthan a clock cycle at the nominal voltage and temperature. The samerequirement must be met when an asynchronous circuit block is embeddedinto a synchronous circuit system. If the requirement is not satisfieddue to the delay in response of the asynchronous circuit block, theasynchronous circuit block needs to be redesigned or the frequency ofthe global clock needs to be lowered. The above is disclosed in U.S.Pat. No. 5,063,536.

SUMMARY OF THE INVENTION

However, trouble typically results in redesigning the asynchronouscircuit block to meet the above-mentioned minimum requirement. Moreover,even if the requirement could be met by lowering the frequency of theglobal clock, another problem must arise, in that the throughput of thewhole synchronous circuit system decreases.

In consideration of these and/or other issues, an exemplary embodimentof the present invention provides a synchronous/asynchronous interfacecircuit to embed an asynchronous circuit block in a synchronous circuitsystem without decreasing the throughput of the entire synchronouscircuit system and without redesigning the asynchronous circuit block tomeet the aforementioned minimum requirement, and an electronic deviceincluding the asynchronous circuit block, the synchronous circuit systemand the synchronous/asynchronous interface circuit.

In order to address or solve the above, the synchronous/asynchronousinterface circuit according to an exemplary embodiment of the presentinvention controls an interface between a synchronous circuit and aasynchronous circuit, and includes a finite state machine to control, inan event-driven fashion, an access cycle operated between thesynchronous circuit and the asynchronous circuit, and a detectioncircuit to detect the beginning of the access cycle. In interfacing withthe asynchronous circuit, the finite state machine controls the accesscycle by transiting in states handshaking with the asynchronous circuit.Meanwhile, in interfacing with the synchronous circuit, the finite statemachine controls the access cycle by transiting in states synchronizingwith a global clock supplied from the synchronous circuit. Such aconfiguration enables embedding of the asynchronous circuit into thesynchronous circuit as a part of an entire synchronous circuit systemwithout decreasing the throughput of the whole synchronous circuitsystem, since the asynchronous circuit operates as a synchronous circuitat the interface with the synchronous circuit.

Preferably, the detection circuit to detect the beginning of the accesscycle can include a differential circuit to differentiate a global clocksupplied from a synchronous circuit and a through-latch circuit to latcha control signal that starts the access cycle when the logic state ofeither the rising-edge signal or the falling-edge signal of the globalclock, which is output from the differential circuit, changes. Becauseit is asynchronous to the global clock for the asynchronous circuit tostart the access cycle, the transition from a meta-stable state to astable state can be swiftly carried out, even when the start of theaccess cycle is coincident with the logic state change of the globalclock.

Preferably, the synchronous/asynchronous interface circuit of thepresent invention can further include an address latch circuit to latchthe address signal output from the asynchronous circuit to thesynchronous circuit and a data latch circuit to latch the data signaloutput from the asynchronous circuit to the synchronous circuit. Thetiming to output the address signal latched by the address latch circuitand to output a data signal latched by the data latch circuit into thesynchronous circuit is controlled by the finite state machine insynchronization with the global clock. Such a configuration enables thetiming of outputting the address signals and the date signals from theasynchronous circuit to the synchronous circuit to be synchronized withthe global clock.

Preferably, the through-latch circuit included in the detection circuitthat detects the beginning of the access cycle can be configured to beracing-free. By configuring the through-latch circuit in a racing-freecondition, the state transitions of the finite state machine can bestabilized.

An electronic device according to an exemplary embodiment of the presentinvention is provided with the above-mentioned synchronous/asynchronousinterface circuit. Such a configuration can provide a high-gradeelectronic device utilizing the characteristics of thesynchronous/asynchronous interface circuit.

According to an exemplary embodiment of the present invention, asynchronous/asynchronous interface circuit operates as a part of asynchronous circuit interfacing an asynchronous circuit with thesynchronous circuit. Therefore, the asynchronous circuit can be embeddedinto a globally synchronous circuit system as a part of the systemwithout either decreasing the throughput of the system or re-designingthe asynchronous circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic that shows an entire composition of asynchronous/asynchronous interface circuit according to an exemplaryembodiment of the present embodiment;

FIG. 2 is a schematic that shows input/output signals between asynchronous CPU and a synchronous bus;

FIG. 3 is a schematic that shows input/output signals between anasynchronous CPU and the synchronous/asynchronous interface circuit;

FIG. 4 is a schematic that shows a bus cycle of the synchronous CPU;

FIG. 5 is a schematic that shows a bus cycle of the synchronous CPU;

FIG. 6 is a schematic showing state transitions of a finite statemachine;

FIG. 7 is a schematic showing the handshaking of a read cycle;

FIG. 8 is a schematic that illustrates a read cycle of the asynchronousCPU;

FIG. 9 is a schematic showing the handshaking of a write cycle;

FIG. 10 is a schematic that illustrates a write cycle of theasynchronous CPU;

FIG. 11 is a schematic that shows composition of thesynchronous/asynchronous interface circuit;

FIG. 12 is a schematic that illustrates a read cycle of the asynchronousCPU;

FIG. 13 is a schematic that illustrates a write cycle of theasynchronous CPU;

FIG. 14 is a schematic that shows connection of the differentialcircuit;

FIG. 15 is a schematic that illustrates composition of the differentialcircuit;

FIG. 16 is a schematic that shows differential waves output from thedifferential circuit;

FIG. 17 is a schematic showing connection of a through latch circuit;

FIG. 18 is a schematic that illustrates composition of the through latchcircuit;

FIG. 19 is a schematic that illustrates composition of a bus cyclestart-detection circuit;

FIG. 20 is a schematic that illustrates timing for starting a bus cycle;

FIG. 21 is a schematic that illustrates composition of a PK outputcircuit; and

FIG. 22 is a signal transition graph of the bus cycle.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following, exemplary embodiments of the present invention aredescribed with reference to the accompanying drawings.

FIG. 1 illustrates an entire composition of a synchronous/asynchronousinterface circuit according to an exemplary embodiment of the presentinvention. A synchronous/asynchronous interface circuit 20 lies betweenan asynchronous CPU 10 and a synchronous bus 30, linking the two. Thesynchronous/asynchronous interface circuit 20 is a circuit that makesthe asynchronous CPU 10 apparently act as a synchronous CPU 40 for thesynchronous bus 30. The synchronous/asynchronous interface circuit 20operates in two ways. On one hand, it operates as a synchronous circuitunit driven by a global clock signal (CLK signal) at a point ofconnection with the synchronous bus 30. The synchronous/asynchronousinterface circuit 20 satisfies the above-mentioned minimum requirementby the handshaking with the asynchronous CPU 10 regardless of thetransition inner states. The inner states of thesynchronous/asynchronous interface circuit 20 that are involved in theconnection with the synchronous bus 30 transit in synchronization with aglobal clock. By configuring a through latch circuit to hold the innerstates in a race-free condition, the synchronous/asynchronous interfacecircuit 20 shifts quickly from a meta-stable state to a stable state,even when the timing for handshaking with the asynchronous CPU 10, whichis totally asynchronous with the global clock, competes with the timingof the global clock. On the other hand, at a point of connection withthe asynchronous CPU 10, the synchronous/asynchronous interface circuit20 operates as an asynchronous finite state machine, which is free fromthe global clock, and transits from one state to another by thehandshaking with the asynchronous CPU 10.

The term “synchronous circuit” as used herein means a circuit designedto work based on a global clock for central control of the system. Thesynchronous bus 30 and the synchronous CPU 40 are synchronous circuits.The term “asynchronous circuit” as used herein means a circuit designedso that its minimal function circuits (processes) conduct distributedcontrol independently or dependently from, and locally cooperating with,one another without using a global clock. In the asynchronous circuit,the minimal function circuits are controlled in an event-driven fashionand operate only when it is decided as necessary to operateindependently or dependently. In other words, a minimal function circuitcan operate in parallel with and independently from the other minimalfunction circuits, and it does not need to wait for the other minimalfunction circuits to complete their processing in order for itself tostart processing. A minimal function circuit can start processingwhenever it is prepared to execute a desired process. The asynchronousCPU 10 is an asynchronous circuit.

FIG. 2 shows input/output signals between the synchronous CPU 40 and thesynchronous bus 30. FIG. 3 shows input/output signals between theasynchronous CPU 10 and the synchronous/asynchronous interface circuit20. The term “X_signal” as used herein means that the X_signal is a lowactive signal. FIG. 4 illustrates a bus cycle of the synchronous CPU 40acted by the synchronous/asynchronous interface circuit 20. As shown inFIG. 4, the bus cycle of the synchronous CPU 40 has four states: S1, S2,S3, and S4, in this order. Each of the states is encoded by a PK signalor a PL signal. More specifically, the state transits to S1 when PK=0and PL=0, to S2 when PK=1 and PL=0, to S3 when PK=1 and PL=1, and to S4when PK=0 and PL=1. While a WAIT_signal is omitted here for simplicity,when the synchronous CPU 40 accesses a low-speed device, it senses aWAIT_signal at the rising of a CLK signal in state S3. If WAIT_(—)=0,the period of state S3 is extended by one clock as shown in FIG. 5.Although a bus cycle having four states is described here, this is notintended to limit the present invention. Furthermore, although in thepresent exemplary embodiment a bus cycle is described as an access cycleexchanged between an asynchronous CPU and a peripheral device, this isnot intended to limit the present invention either.

FIG. 6 shows state transitions of the bus cycle of the synchronous CPU40. When the synchronous CPU 40 executes the inner cycle inside the CPUwithout accessing the synchronous bus 30, the bus cycle is not executedand state S1 is maintained (PK=PL=0). If the synchronous CPU 40 accessesthe synchronous bus 30, and thereby getting the bus cycle started, thestate transits to state S2 (PK=1, PL=0) in half a clock and then tostate S3 (PK=PL=1) in another half a clock. In state S3, the WAIT_signalis checked at the rising of the CLK signal. When WAIT_(—)=0, the periodof state S3 is extended for one more clock. When WAIT_(—)=1 at therising of the CLK signal, the state shifts from state S3 to state S4(PK=0, PL=1), and then returns to state S1 (PK=PL=0) in another half aclock. As thus described, the synchronous CPU 40 accesses thesynchronous bus 30 by running the bus cycle in synchronization with therising or falling timing of the CLK signal.

FIGS. 7 and 8 show the handshaking between the asynchronous CPU 10 and aperipheral device 50 when the asynchronous CPU 10 executes a read cyclewithout the synchronous/asynchronous interface circuit 20 therebetween.After outputting an address signal on an address bus a15-00 at a timingt1, the read cycle of the asynchronous CPU 10 begins by setting ard_signal to active low at a timing of t2. Meanwhile, the read cycle ofthe peripheral device 50 begins when the rd_signal turns to active low.The peripheral device 50 outputs addressed number data onto the data busd7-0 at a timing t3, and further turns an ack_signal to active low at atiming t4. As the ack signal becomes active low, the asynchronous CPU 10detects the outputting of the desired data onto the data bus d7-0 andloads the data into the inner register. The asynchronous CPU 10 sets therd_signal to negative high at a timing t5 when the writing of the datainto the inner register is terminated, thereby announcing the completionof the read cycle. In response the peripheral device 50 sets theack_signal to negative high at a timing t6 and confirms the completionof the read cycle. After the ack_signal turns to negative high, theasynchronous CPU 10 stops outputting the address data to the address busa15-00 at a timing t7, which completes the read cycle. This way the readcycle of the asynchronous CPU 10 and the peripheral device 50 isaccomplished by the four-phase handshaking using the rd_ andack_signals.

FIGS. 9 and 10 show the handshaking between the asynchronous CPU 10 andthe peripheral device 50 when the asynchronous CPU 10 executes the writecycle without the synchronous/asynchronous interface circuit 20therebetween. After outputting an address signal onto an address busa15-00 at a timing t1, and then outputting data onto the data bus d7-0at a timing t2 with a slight delay from t1, the write cycle of theasynchronous CPU 10 begins by setting a wr_signal to active low at atiming t3. Meanwhile, the peripheral device 50, upon receiving a writerequest from the asynchronous CPU 10, writes designated data (d7-0) intoa designated address (a15-00) and sets the ack signal to active low at atiming t4. In response to the transition of the ask_signal to activelow, the asynchronous CPU 10 sets the wr_signal to negative high at atiming t5 so as to announce completion of the write cycle and thenterminates outputting data onto the data bus d7-0. Receiving theannouncement of completion, the peripheral device 50 sets the ack_signalto negative high at a timing t6 and confirms the completion. With theask_signal turning to negative high, the asynchronous CPU 10 detects thecompletion of the write cycle and terminates the outputting of theaddress data to the address bus a15-00 at a timing t7, and therebycompleting the write cycle. As thus described, the write cycle betweenthe asynchronous CPU 10 and the peripheral device 50 is accomplished bythe four-phase handshaking using the rd_ and ack_signals.

FIG. 11 is a composition of the synchronous/asynchronous interfacecircuit 20. As shown in the diagram, the synchronous/asynchronousinterface circuit 20 mainly includes a differential circuit 21 todifferentiate the CLK signal so as to produce rising edge and fallingedge signals of the CLK signal, a finite state machine 22 to control abus cycle operated between the asynchronous CPU 10 and the synchronousbus 30 in an event-driven fashion, an address latch circuit (A-latchcircuit) 23 to latch address data output from the asynchronous CPU 10 tothe synchronous bus 30, and a data latch circuit (D-latch circuit) 24 tolatch data input and output between the asynchronous CPU 10 and thesynchronous bus 30. The finite state machine 22 is an event-drivensystem to control the timing, in accordance with the bus cycle, to inputand output bus control signals, address signals, and data signalsexchanged between the asynchronous CPU 10 and the synchronous bus 30. Inthe interface with the asynchronous CPU 10, the finite state machine 22controls the bus cycle by transiting states to asynchronous by thehandshaking with the asynchronous CPU 10, while in the interface withthe synchronous bus 30, the finite state machine 22 controls the buscycle by transiting states in synchronization with a global clocksupplied from the synchronous bus 30.

Since it is necessary that the synchronous/asynchronous interfacecircuit 20 acts as a peripheral device for the asynchronous CPU 10, thesynchronous/asynchronous interface circuit 20 receives, on behalf of theperipheral device, the rd_signal or the wr_signal coming from theasynchronous CPU 10 and outputs the corresponding ask_signal onto theasynchronous CPU 10. Meanwhile, because the synchronous/asynchronousinterface circuit 20 needs to operate as the synchronous CPU 40 for thesynchronous bus 30, the synchronous/asynchronous interface circuit 20outputs, on behalf of the asynchronous CPU 10, the RD_signal, WR_signal,PK signal, and PL signal to the synchronous bus 30, and receives, onbehalf of the asynchronous CPU 10, the WAIT_signal output from thesynchronous bus 30. The timing to output the bus control signals(RD_signal, WR_signal) and the clock signals (PK signal, PL signal) thatcome from the finite state machine 22 is synchronized with the risingsignal or falling signal of the global clock coming from thedifferential circuit 21. Similarly, the timing to output the addresssignals from the A-latch circuit 23 to the synchronous bus 30 and thetiming to output the data signals from the D-latch circuit 24 to thesynchronous bus 30 are controlled by the finite state machine 22 so thatthe timings are synchronized with the rising signal or the fallingsignal of the global clock.

Mounted inside the finite state machine 22 is a bus cyclestart-detection circuit (not shown) to detect the start of the buscycle. The circuit detects the start of the bus cycle when the rd_signalor the wr_signal output from the asynchronous CPU 10 transits to activelow. Then the state transits every half a clock as shown in theabove-described drawing of state transitions (FIG. 6), and by followinga communication procedure preallotted to each state, the bus cycle iscontrolled. The bus cycle start-detection circuit is described in detailbelow in reference to FIG. 19.

FIG. 12 shows handshaking to execute a read cycle between theasynchronous CPU 10 and the peripheral device 50 through thesynchronous/asynchronous interface circuit 20. After an address isoutput onto the address bus a15-00 at a timing t2, the read cycle of theasynchronous CPU 10 begins by setting the rd_signal to active low at atiming t3. The bus cycle does not start at a timing t1, which precedesthe timing t2, since the rd_signal is still negative high at the timingt1. When the rd_signal is sensed at a timing t4, which is one clock pastthe timing t1, the finite state machine 22 detects the beginning of thebus cycle because the rd_signal is now turned active low. At a timingt5, which is almost the same time as the timing t4, the states shift atevery half a clock from S1, to S2, S3, and S4 in this order, and therebythe bus cycle is executed. This means that the read cycle is executed bythe synchronous CPU 40. The A-latch circuit 23 latches the address dataoutput onto the address bus a15-00 and outputs the latched address dataonto the address bus A15-00 at the timing t5 at which the bus cyclebegins. This makes the synchronous CPU 40 start the read cycle. Then,half a clock later at a timing t6 when the CLK signal rises, the finitestate machine 22 shifts from state S1 to state S2 and sets the RD_signalto active low. In response to the transition of the RD_signal to activelow, a peripheral device (not shown) coupled to the synchronous bus 30outputs the addressed number data onto the data bus D7-0 half a clocklater at a timing t7 when the CLK signal falls. In case of the readcycle, the D-latch circuit 24 passes data signals onto the data bus D7-0without latching the data signals. At this point, the finite statemachine 22 is in state S3.

The finite state machine 22 senses the WAIT_signal half a clock later att8 when the CLK signal rises, confirms the signal to be negative high,and shifts from state S3 to state S4. As the synchronous/asynchronousinterface circuit 20 needs to apparently act as a peripheral device forthe asynchronous CPU 10, the synchronous/asynchronous interface circuit20 sets the ack_signal to active low at a timing t8 in order to notifythe asynchronous CPU 10 of the outputting of the desired data onto thedata bus d7-0. Upon-detecting the ack_signal being active low, theasynchronous CPU 10 writes into the inner register the data being outputonto the data bus d7-0 and sets the rd_signal to negative high, therebyannouncing the completion of the read cycle. Upon receiving this, thefinite state machine 22 sets the RD_signal to negative high andannounces completion of the read cycle to the peripheral device. As therd_signal is set to negative high, the finite state machine 22 sets theack_signal to negative high and confirms completion of the read cycle.After the ack_signal turns to negative high, the asynchronous CPU 10terminates the outputting of address data onto the address bus a15-00 ata timing t9 and completes the read cycle of the asynchronous CPU 10.When the CLK signal falls at a timing t10, half a clock after the timingt8, the outputting of the address data onto the address bus A15-00 bythe synchronous/asynchronous interface circuit 20 is terminated, andthus the read cycle by the synchronous CPU 40 is completed.

FIG. 13 illustrates the handshaking to execute a write cycle between theasynchronous CPU 10 and the peripheral device 50 through thesynchronous/asynchronous interface circuit 20. After the address isoutput at a timing t2 onto the address bus a15-00, and then the data areoutput onto the data bus d7-0 at a timing t3, which is slightly afterthe timing t2, the write cycle of the asynchronous CPU 10 starts bysetting the wr_signal to active low at a timing t4. The bus cycle doesnot begin at a timing t1, which precedes the timing t2, since thewr_signal is negative high. Upon sensing the wr_signal at a timing t5,which is one clock past the timing t1, the finite state machine 22detects the start of the bus cycle since the wr_signal is now turnedactive low. At a timing t6, which is almost the same time as the timingt5, the finite state machine 22 makes the states shift from S1, to S2,S3, and S4 in this order every half a clock, and executes the bus cycle.This means that the write cycle is executed by the synchronous CPU 40.The A-latch circuit 23 latches the address data output onto the addressbus a15-00 and outputs the latched address data onto the address busA15-00 at a timing t6 at which the bus cycle begins. This triggers thewrite cycle by the synchronous CPU 40. The finite state machine 22 thentransits from state S1 to state S2 half a clock later at a timing t7when the CLK signal rises. The D-latch circuit 24 latches the dataoutput onto the data bus d7-0 and outputs the latched address data ontothe data bus D7-0 at a timing t7 when the finite state machine 22transits from state S1 to state S2. Then, half a clock later, at atiming t8 when the CLK signal falls, the finite state machine 22 shiftsfrom state S2 to state S3 and sets the WR_signal to active low.

The finite state machine 22 senses the WAIT_signal half a clock later ata timing t9 when the CLK signal rises, confirms the signal to benegative high, and shifts from state S3 to state S4. Since thesynchronous/asynchronous interface circuit 20 needs to apparently act asthe peripheral device for the asynchronous CPU 10, thesynchronous/asynchronous interface circuit 20 sets the ack_signal toactive low at the timing t9 when the writing of the data is completed bya peripheral device (not shown) coupled to the synchronous bus 30, andthen notifies the asynchronous CPU 10 that the data writing iscompleted. The asynchronous CPU 10 then sets the wr_signal to negativehigh and announces completion of the write cycle. In response, thefinite state machine 22 sets the WR_signal to negative high andannounces completion of the read cycle to the peripheral device. Whenthe wr_signal is set to negative high, the finite state machine 22confirms completion of the write cycle by setting the ack_signal tonegative high. After the ack_signal is set to negative high, theasynchronous CPU 10 then terminates the outputting of address data ontothe address bus a15-00 at a timing t10, and thereby completing the writecycle by the asynchronous CPU 10. Half a clock after the timing t9, at atiming t11 when the CLK signal falls, the outputting of the address dataonto the address bus A15-00 by the synchronous/asynchronous interfacecircuit 20 is terminated, and thus the write cycle by the synchronousCPU 40 is completed.

As described, when the synchronous/asynchronous interface circuit 20detects the rd_signal or wr_signal being active low with the CLK signalat its falling edge, the synchronous/asynchronous interface circuit 20shifts from the inner cycle to the bus cycle and makes time adjustmentso that all of the bus control signals, data signals, and addresssignals output from the synchronous/asynchronous interface circuit 20 tothe synchronous bus 30 are synchronized with the synchronous bus 30,enabling the connection of the asynchronous CPU 10 to the synchronousbus 30. The communication procedures for each state (S1, S2, S3, and S4)in the read cycle or the write cycle are predetermined. Thesynchronous/asynchronous interface circuit 20 can make the asynchronousCPU 10 apparently act as the synchronous CPU 40 for the synchronous bus30, by executing the above-described communication procedures inaccordance with the timings synchronized with the rising or fallingsignal of the CLK signal.

FIG. 14 is a diagram showing connection of the differential circuit 20,and FIG. 15 shows its circuit. FIG. 16 depicts differential waves of theCLK signal of the differential circuit 21. As shown, the differentialcircuit 21 differentiates the CLK signal so as to output R-edge andF-edge signals having a minute pulse width at their rising and fallingedges. FIG. 17 is a diagram showing connection of a through latchcircuit 60, and FIG. 18 shows its circuit. Referring to FIG. 18, TG1 andTG2 are transfer gates including an N-channel transistor and a P-Channeltransistor, respectively. TG1 is conductive when the se1 signal is highand the se1_signal is low, and the gate electric potential of aninverter INV 1 is almost the same as the electric potential of the inputsignal din. The electric potential of the input signal din goes throughTG1, INV1, to INV3, and affects the output signal q, while it goesthrough TG1 to INV1 and affects the output signal q_. Here, when the se1signal transits to low and the se1_signal transits to high, TG1 becomesnon-conductive and TG2 becomes conductive, resulting in formation of afeedback loop of INV1, INV2, TG2, and INV1. Then, the electric potentialof the output signal q at that time is latched.

FIG. 19 shows a composition of a bus cycle start-detection circuit 25.The bus cycle start-detection circuit 25 mainly includes thedifferential circuit 21 and through latch circuits 61 and 62. Thecircuit composition of the through latch circuits 61 and 62 arebasically the same as that of the through latch circuit 60 mentionedabove. An F-edge signal as a se1 signal is input into the through latchcircuits 61 and 62, while an inverted signal of the F-edge signal as ase1_signal is input via an inverter 71. Further, an inverted rd_signalor wr_signal as an input signal din is input through an inverter 72 or73 into the through latch circuit 61 or 62, respectively. Output signalsof the through latch circuit 61 are go (READ CYCLE) and go (READCYCLE)_. Output signals of the through latch 62 are go (WRITE CYCLE) andgo (WRITE CYCLE)_.

In order for the finite state machine 22 to transit from the inner cycleto the bus cycle, the rd_signal or the wr_signal needs to be detected asactive low at the falling edge of the CLK signal. Because the CLK signalsupplied from the synchronous bus 30 to the synchronous/asynchronousinterface circuit 20 is not synchronized with the rd_signal and thewr_signal, which are supplied from the asynchronous CPU 10 to thesynchronous/asynchronous interface circuit 20, a delicate timing mayoccur. In other words, the rd_signal or the wr_signal possibly changesto active low at exactly the same time as the CLK signal falls. If therd_signal or the wr_signal changes at exactly the same time as theF-edge signal transits from high to low, the signal level latched by thethrough latch circuits 61 and 62 can either be high or low.

FIG. 20 illustrates a timing at which the bus cycle start-detectioncircuit 25 starts the bus cycle by detecting the rd_signal as active lowwhen the CLK signal falls. With this timing as shown in the drawing, thebus cycle fails to start at the initial fall of the CLK signal andsucceeds to start at the next fall. In the drawing, at the delicatetiming when the rd_signal transits from high to low at exactly the sametime as the F-edge signal transits from high to low, a single glitch mayoccur on the output go (READ CYCLE) signal and go (READ CYCLE)_signalsof the through latch circuit 61, having a peak for driving the lattergate. Since the pulse width of this glitch is so narrow that itdisappears by the time when the CLK signal rises, it does not create anyproblem in the state transition control of the synchronous/asynchronousinterface circuit 20. Moreover, so as not to generate racing, thethrough latch circuits 61 and 62 are designed and verified to berace-free.

As described, if at the falling of the CLK signal an F-edge signallatches the inverted rd_signal to be high, high is output to the go(READ CYCLE) signal, and S1 (inner cycle) transits to S1 (bus cycle).Since an address to be accessed is output to the address bus (a15-00)from the asynchronous CPU 10 at this time, this is output to the addresssignal of the synchronous bus at this timing. While FIG. 20 shows thetiming to start the bus cycle of the read cycle, the same is true withthe timing to start the bus cycle of the write cycle. It means that ifat the falling of the CLK signal the F-edge signal latches the invertedwr_signal to be high, high is output to the go (WRITE CYCLE) signal andS1 (inner cycle) transits to S1 (bus cycle), while S1 is held if low.

Then, if at the rising of the CLK signal an R-edge signal latches the go(READ CYCLE) signal to be high, high is output to the PK signal and S1transits to S2, while S1 is maintained if low. Further, if at thefalling of the CLK signal the F-edge signal latches the PK signal to behigh, high is output to the PL signal and S2 transits to S3, while S2 ismaintained if low. Furthermore, if at the rising of the CLK signal theR-edge signal latches the logical multiply (AND) of the PL signal and aWAIT_signal to be high, low is output to the PK signal and S3 transitsto S4, while S3 is maintained if low. As thus described, timing of thestate transition from S3 to S4 depends on the WAIT_signal. As long asthe WAIT_signal is low, the PK signal does not turn to low, andtherefore S3 is maintained. Then, if at the falling of the CLK signalthe F-edge signal latches the PL signal to be high, low is output to thePL signal, and S4 transits to S1. The generation of the signals involvedin the state transition of the read cycle has been described. FIG. 22 isa signal transition graph (STG) of the asynchronous CPU 10 and thesynchronous/asynchronous interface. circuit 20 that also shows the statetransition of the write cycle.

As herein described, the synchronous/asynchronous interface circuit 20according to the present exemplary embodiment makes it possible to embedthe asynchronous CPU 10 into an entire circuit system as a part of thesystem, without decreasing the throughput of the entire synchronouscircuit system. It is therefore not necessary to redesign theasynchronous CPU 10 in order to satisfy the minimum requirement.Further, when the asynchronous CPU 10 is already designed and requiredto be reused as an IP in a certain area, the connection design and theverification can be carried out in an extremely short period of time byadopting the synchronous/asynchronous interface circuit 20 according tothe present embodiment. The level of verification largely depends on thefact that the synchronous/asynchronous interface circuit 20 includes afinite state machine and handshaking, and is attributed to the fact thatthe input/output signals of all the circuit blocks involved in thehandshaking are acknowledged without fail.

The synchronous/asynchronous interface circuit of the exemplaryembodiment of the present invention is applicable for various electronicdevices, such as mobile phones, camcorders, mobile personal computers(personal digital assistants), head mount displays, and projectors aspart of their circuit components, for example, and can be also used. forvarious applications, such as system-on-chip or system-on-panelproducts.

1. A synchronous/asynchronous interface circuit that interfaces anasynchronous circuit with a synchronous circuit, comprising: a finitestate machine having more than two states that controls access cyclesbetween the synchronous circuit and the asynchronous circuit in anevent-driven fashion; and a detection circuit that detects beginnings ofthe access cycles, the finite state machine transiting the more than twostates to control the access cycles while both handshaking with theasynchronous circuit and synchronizing with a global clock supplied fromthe synchronous circuit.
 2. The synchronous/asynchronous interfacecircuit according to claim 1, the detection circuit including: adifferential circuit that outputs differential signals, each of thedifferential signals corresponding to one of a rising edge and a fallingedge of the global clock; and a through-latch circuit that latchescontrol signals to start the access cycles, only when the differentialcircuit outputs the differential signals.
 3. Thesynchronous/asynchronous interface circuit according to claim 2, furthercomprising: an address latch circuit that latches address signals outputfrom the asynchronous circuit to send to the synchronous circuit; and adata latch circuit that latches data signals output from theasynchronous circuit to send to the synchronous circuit, timing for thesynchronous/asynchronous interface circuit to output both the addresssignals and data signals into the synchronous circuit being controlledrespectively by the finite state machine in synchronization with theglobal clock.
 4. The synchronous/asynchronous interface circuitaccording to claim 2, the through-latch circuit being configured to beracing-free.
 5. A synchronous/asynchronous interface circuit thatinterfaces an asynchronous circuit with a synchronous circuit, thesynchronous/asynchronous interface circuit comprising: a finite statemachine having more than two states that controls access cycles betweenthe asynchronous circuit and the synchronous circuit in an event-drivenfashion; and a detection circuit that detects beginnings of the accesscycles, the finite state machine transiting the more than two states to:control the access cycles by handshaking with the asynchronous circuit,and control the access cycles by synchronizing with a global clocksupplied from the synchronous circuit.
 6. A synchronous/asynchronousinterface circuit that interfaces an asynchronous circuit with asynchronous circuit, the synchronous/asynchronous interface circuitcomprising: a finite state machine having more than two states thatcontrols access cycles between the asynchronous circuit and thesynchronous circuit in an event-driven fashion; and a detection circuitthat detects beginnings of the access cycles, the finite state machinetransiting the more than two states to: control the access cycles byhandshaking with the asynchronous circuit during a period in which afirst interface between the finite state machine and the asynchronouscircuit is carried out, and control the access cycles by synchronizingwith a global clock supplied from the synchronous circuit during aperiod in which a second interface between the finite state machine andthe synchronous circuit is carried out.